The present invention generally relates to data processing interfaces and more particularly, to an interface between a central processing unit and a programmable logic device.
In some input/output channel applications, data transferred between the channels and a central processing unit may be lost due to data conflicts or data being overwritten during transfer. The data transfer may be organized on a packet basis and transferred in data clusters according to the type of data flowing and the type of input/output channels used. In some instances, the channels use asynchronous data flow.
It is known to employ a system that provides a common interface to a central processing unit among a plurality of input/output channels using a random access memory. In some instances, the random access memory includes two ports where one port is dedicated exclusively to communicating with the central processing unit and the other port is dedicated to communicating exclusively to a controller connected to the input/output channel. It is further known to employ the port associated with the central processing unit for use with one memory address area while using the port associated with the controller with a different memory address area during data transfer. Generally these two different address areas are associated with different areas within an address map.
One example of a prior art data processing system may be seen in U.S. Pat. No. 5,881,228 to Atkinson et al. Atkinson et al. teach the use of a dual port RAM chip where one port is dedicated to communicating with a host processor and the other port is dedicated to interfacing with a microcontroller.
As can be seen, there is a need for a data bus interface between a central processing unit and an input/output channel that mitigates data loss during transfer.